IDT7009L20PFI【PDF 1/17 页】IC SRAM 1MBIT 20NS 100TQFP

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Features

HIGH-SPEED

128K x 8 DUAL-PORT

STATIC RAM

IDT7009L

◆

True Dual-Ported memory cells which allow simultaneous

than one device

reads of the same memory location

◆

M/ S = V IH for BUSY output flag on Master,

◆

High-speed access

M/ S = V IL for BUSY input on Slave

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

◆

Interrupt Flag

On-chip port arbitration logic

◆

Low-power operation

– IDT7009L

Active: 1W (typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT7009 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

◆

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

R/ W L

CE 0L

CE 1L

OE L

R/ W R

CE 0R

CE 1R

OE R

BUSY L

I/O 0-7L

(1,2)

I/O

Control

I/O

Control

I/O 0-7R

BUSY R

(1,2)

A 16L

A 0L

Address

Decoder

128Kx8

MEMORY

ARRAY

7009

Address

Decoder

A 16R

A 0R

INT L

M/ S

INT R

SEM L

(2)

CE 0L

CE 1L

OE L

R/ W L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

(1)

CE 0R

CE 1R

OE R

R/ W R

SEM R

(2)

4839 drw 01

NOTES:

1. BUSY is an input as a Slave (M/ S = V IL ) and an output when it is a Master (M/ S = V IH ).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

?2008 Integrated Device Technology, Inc.

NOVEMBER 2008

DSC-4839/5

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